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1 features ? 32-mbit flash and 4-mbit/8-mbit sram single 66-ball (8 mm x 10 mm x 1.2 mm) cbga package 2.7v to 3.3v operating voltage flash 2.7v to 3.3v read/write access time ? 70 ns sector erase architecture ? sixty-three 32k wordsectors with individual write lockout ? eight 4k word sectors with individual write lockout fast word program time ? 15 s sector erase time ? 300 ms suspend/resume feature for erase and program ? supports reading and programming from any sector by suspending erase of a different sector ? supports reading any word by suspending programming of any other word low-power operation ?12 ma active ? 13 a standby data polling, toggle bit, ready/busy for end of program detection vpp pin for write protection and accelerated program/erase operations reset input for device initialization sector lockdown support top or bottom boot block configuration available 128-bit protection register minimum 100,000 erase cycles sram 4-megabit (256k x 16)/8-megabit (512k x 16) 2.7v to 3.3v v cc 70 ns access time fully static operation and tri-state output 1.2v (min) data retention industrial temperature range device number flash boot location flash plane architecture sram configuration at52br3224a bottom 32m 256k x 16 at52br3224at top 32m 256k x 16 AT52BR3228A bottom 32m 512k x 16 AT52BR3228At top 32m 512k x 16 32-megabit flash + 4-megabit/ 8-megabit sram stack memory at52br3224a at52br3224at AT52BR3228A AT52BR3228At preliminary rev. 3338b?stkd?6/03
2 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 pin configuration at52br3224a(t)/ AT52BR3228A(t) (top view) pin name function a0 - a17 flash/sram common address input for 4m sram a0 - a18 flash/sram common address input for 8m sram a19 - a20 flash address input ce flash chip enable oe flash output enable we flash write enablee reset flash reset rdy/busy flash ready/busy output vpp flash power supply for accelerated program/erase operations vcc flash power gnd flash ground i/o0 - i/o15 data inputs/outputs nc no connect slb sram lower byte sub sram upper byte svcc sram power sgnd sram ground scs1 sram chip select 1 scs2 sram chip select 2 swe sram write enable soe sram output enable a b c d e f g h 1 23456789101112 nc nc nc nc a20 a16 we sgnd nc slb a18 nc a11 a8 rdy/busy res vpp sub a17 a5 a15 a10 a19 soe a7 a4 a14 a9 i/o11 a6 a0 a13 i/o15 i/o13 i/o12 i/o9 a3 ce a12 swe i/o6 scs2 i/o10 i/o8 a2 gnd gnd i/o14 i/o4 svcc i/o2 i/o0 a1 oe nc i/o7 i/o5 vcc i/o3 i/o1 scs1 nc nc nc nc nc
3 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 block diagram description the at52br3224a(t) combines a 32-megabit flash (2m x 16) and a 4-megabit sram (orga- nized as 256k x 16) in a stacked 66-ball cbga package. the AT52BR3228A(t) combines a 32-megabit flash (2m x 16) and an 8-megabit sram (organized as 512k x 16) in a stacked 66-ball cbga package. the stacked modules operate at 2.7v to 3.3v in the industrial temper- ature range. 32-mbit flash 4/8-mbit sram address data reset ce rdy/busy scs1 scs2 we swe soe oe absolute maximum ratings temperature under bias.................................. -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -55 c to +150 c all input voltages except v pp and reset (including nc pins) with respect to ground .....................................-0.2v to +3.3v voltage on v pp with respect to ground ..................................-0.2v to + 6.25v voltage on reset with respect to ground ...................................-0.2v to +13.5v all output voltages with respect to ground .....................................-0.2v to +0.2v dc and ac operating range at52br3224a(t)/3228a(t)-70 operating temperature (case) industrial -40 c - 85 c v cc power supply 2.7v to 3.3v
4 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 32-megabit flash memory description the 32-megabit flash is a a 2.7-volt memory organized as 2,097,152 words of 16 bits each. the memory is divided into 71 sectors for erase operations. the device has ce and oe con- trol signals to avoid any bus contention. this device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. the device powers on in the read mode. command sequences are used to place the device in other operation modes such as program and erase. the device has the capability to protect the data in any sector (see ?sector lockdown? section). to increase the flexibility of the device, it contains an erase suspend and program suspend feature. this feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. the end of a program or an erase cycle is detected by the ready/busy pin, data polling or by the toggle bit. the vpp pin provides data protection. when the v pp input is below 0.4v, the program and erase functions are inhibited. when v pp is at 0.9v or above, normal program and erase opera- tions can be performed. a six-byte command (enter single pulse program mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. after entering the six-byte code, only single pu lses on the write control lines are required for writing into the device. this mode (single pu lse word program) is exited by powering down the device, or by pulsing the reset pin low for a minimum of 500 ns and then bringing it back to v cc . erase, erase suspend/resume and program suspend/resume commands will not work while in this mode; if entered they will result in data being programmed into the device. it is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code.
5 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 block diagram identifier register status register data comparator output multiplexer output buffer input buffer command register data register y-gating write state machine program/erase voltage switch ce we oe reset rdy/busy vpp vcc gnd y-decoder x-decoder input buffer address latch i/o0 - i/o15 a0 - a20 main memory
6 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 device operation read: the 32-mbit flash memory is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins are asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. command sequences: when the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. in order to perform other device functions, a series of command sequences are entered into the device. the command sequences are shown in the ?command definition in hex? table on page 14 (i/o8 - i/o15 are don?t care inputs for the command codes). the command sequences are written by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . standard microprocessor write timings are used. the address locations used in the command sequences are not affected by entering the command sequences. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation and puts the outputs of the device in a high impedance state. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs. erasure: before a word can be reprogrammed, it must be erased. the erased state of memory bits is a logical ?1?. the entire device can be erased by using the chip erase com- mand or individual sectors can be erased by using the sector erase command. chip erase: the entire device can be erased at one time by using the six-byte chip erase software code. after the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time to erase the chip is t ec . if the sector lockdown has been enabled, the ch ip erase will not erase the data in the sector that has been locked out; it will erase only the unp rotected sectors. after the chip erase, the device will return to the read or standby mode. sector erase: as an alternative to a full chip erase, the device is organized into 71 sec- tors (sa0 - sa70) that can be individually erased. the sector erase command is a six-bus cycle operation. the sector address is latched on the falling we edge of the sixth cycle while the 30h data input command is latched on the rising edge of we . the sector erase starts after the rising edge of we of the sixth cycle. the erase operati on is internally controlled; it will automatically time to completion. the maximum time to erase a sector is t sec . when the sec- tor programming lockdown feature is not enabled, the sector will erase (from the same sector erase command). an attempt to erase a sector that has been protected will result in the oper- ation terminating immediately. word programming: once a memory block is erased, it is programmed (to a logical ?0?) on a word-by-word basis. programming is accomplished via the internal device command reg- ister and is a four-bus cycle operation. the device will automatically generate the required internal program pulses.
7 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 any commands written to the chip during the embedded programming cycle will be ignored. if a hardware reset happens during programming, the data at the location being programmed will be corrupted. please note that a data ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. programming is completed after the specified t bp cycle time. the data polling feature or the toggle bit feature may be used to indicate the end of a program cycle. if the erase/program status bit is a ?1?, the device was not able to verify that the erase or program operation was performed successfully. vpp pin: the circuitry of the 32-mbit flash is designed so that the device cannot be pro- grammed or erased if the v pp voltage is less that 0.4v. when v pp is at 0.9v or above, normal program and erase operations can be performed. the vpp pin cannot be left floating. program/erase status: the device provides several bits to determine the status of a program or erase operation: i/o2, i/o3, i/o5, i/o6 and i/o7. the ?status bit table? on page 13 and the following four sections describe the function of these bits. to provide greater flexibility for system designers, the device contains a programmable configuration register. the configu- ration register allows the user to specify the status bit operation. the configuration register can be set to one of two different values, ?00? or ?01?. if the configuration register is set to ?00?, the part will automatically return to the read mode after a successful program or erase operation. if the configuration register is set to a ?01?, a product id exit command must be given after a successful program or erase operation before the part will return to the read mode. it is impor- tant to note that whether the configuration register is set to a ?00? or to a ?01?, any unsuccessful program or erase operation requires using the product id exit command to return the device to read mode. the default value (after power-up) for the configuration regis- ter is ?00?. using the four-bus cycle set conf iguration register command as shown in the ?command definition in hex? table on page 14, the value of the configuration register can be changed. voltages applied to the reset pin will not alter the value of the configuration regis- ter. the value of the configuration register will affect the operation of the i/o7 status bit as described below. data polling: the device features data polling to indicate the end of a program cycle. if the status configuration register is set to a ?00?, during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on i/o7. once the pro- gram cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sector erase operation, an attempt to read the device will give a ?0? on i/o7. once the program or erase cycle has completed, true data will be read from the device. data polling may begin at any time during the program cycle. please see ?status bit table? on page 13 for more details. if the status bit configuration register is set to a ?01?, the i/o7 status bit will be low while the device is actively programming or erasing dat a. i/o7 will go high when the device has com- pleted a program or erase operation. once i/o7 has gone high, status information on the other pins can be checked. the data polling status bit must be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 1 and 2 on page 11.
8 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 toggle bit: in addition to data polling the device provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the memory will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examin- ing the toggle bit may begin at any time during a program cycle. please see ?status bit table? on page 13 for more details. the toggle bit status bit should be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 3 and 4 on page 12. erase/program status bit: the device offers a status bit on i/o5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. if the status bit is a ?1?, the device is unable to verify that an erase or a word program operation has been successfully performed. if a program (sector erase) command is issued to a pro- tected sector, the protected sector will not be programmed (erased). the device will go to a status read mode and the i/o5 status bit will be set high, indicating the program (erase) opera- tion did not complete as requested. once the erase/program status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. the erase/program status bit is a ?0? while the erase or program operation is still in progress. please see ?status bit table? on page 13 for more details. v pp status bit: the device provides a status bit on i/o3, which provides information regarding the voltage level of the vpp pin. during a program or erase operation, if the voltage on the vpp pin is not high enough to perform the desired operation successfully, the i/o3 sta- tus bit will be a ?1?. once the v pp status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. on the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the v pp status bit will out- put a ?0?. please see ?status bit table? on page 13 for more details. sector lockdown: each sector has a programming lockdown feature. this feature pre- vents programming of data in the designated sectors once the feature has been enabled. these sectors can contain secure code that is used to bring up the system. enabling the lock- down feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; any sector?s usage as a write-protected region is optional to the user. at power-up or reset, all sectors are unlocked. to activate the lockdown for a specific sector, the six-bus cycle sector lockdown command must be issued. once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. sector lockdown detection: a software method is available to determine if program- ming of a sector is locked down. when the devic e is in the software product identification mode (see ?software product identification entry/exit? sections on page 27), a read from address location 00002h within a sector will show if programming the sector is locked down. if the data on i/o0 is low, the sector can be programmed; if the data on i/o0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. the software product identification exit code should be used to return to standard operation.
9 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 sector lockdown override: the only way to unlock a sector that is locked down is through reset or power-up cycles. after power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. erase suspend/erase resume: the erase suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. after the erase suspend co mmand is given, the device requires a maxi- mum time of 15 s to suspend the erase operation. after the erase operation has been suspended, the system can then read data or program data to any other sector within the device. an address is not required during the erase suspend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume command is a one-bus cycle command. the device also supports an erase suspend during a complete chip erase. while the chip erase is suspended, the user can read from any sector within the memory that is pro- tected. the command sequence for a chip erase suspend and a sector erase suspend are the same. program suspend/program resume: the program suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. after the program suspend command is given, the device requires a maximum of 20 s to suspend the programming operati on. after the programming operation has been suspended, the system can then read data from any other word within the device that is not contained in the sector in which the programming operation was suspended. an address is not required during the program suspend operation. to resume the programming operation, the system must write the program resume command. the program suspend and resume are one-bus cycle commands. the command sequence for the erase suspend and program sus- pend are the same, and the command sequence for the erase resume and program resume are the same. product identification: the product identification mode identifies the device and man- ufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. for details, see ?operating modes? on page 20 (for hardware operation) or ?software product identification entry/exit? sections on page 27. the manufacturer and device codes are the same for both modes. 128-bit protection register: the device contains a 128-bit register that can be used for security purposes in system design. the protection register is divided into two 64-bit blocks. the two blocks are designated as block a and block b. the data in block a is non-changeable and is programmed at the factory with a unique number. the data in block b is programmed by the user and can be locked out such that data in the block cannot be repro- grammed. to program block b in the protection register, the four-bus cycle program protection register command must be used as shown in the ?command definition in hex? table on page 14. to lock out block b, the four-bus cycle lock protection register command must be used as shown in the ?command definiti on in hex? table. data bit d1 must be zero during the fourth bus cycle. all other data bits during the fourth bus cycle are don?t cares. to determine whether block b is locked out, the product id entry command is given followed by a read operation from address 80h. if data bit d1 is zero, block b is locked. if data bit d1 is one, block b can be reprogrammed. please see the ?protection register addressing table? on page 15 for the address locations in the protection register. to read the protection register, the product id entry command is given followed by a normal read operation from an address within the protection register. after determining whether block b is protected or not, or reading the protection register, the product id exit command must be given prior to performing any other operation.
10 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 rdy/busy : for the 32-mbit flash memory, an open-drain ready/busy output pin provides another method of detecting the end of a program or erase operation. rdy/busy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. the open-drain connection allows for or-tying of several devices to the same rdy/busy line. please see ?status bit table? on page 13 for more details. hardware data protection: the hardware data protecti on feature protects against inadvertent programs to the device in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) v cc power-on delay: once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) before programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) program inhibit: v pp is less than v ilpp . (e) v pp power-on delay: once v pp has reached 1.65v, program and erase operations are inhibited for 100 ns. input levels: while operating with a 2.7v to 3.6v power supply, the address inputs and control inputs (oe , ce and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to v cc + 0.6v. output levels: for the device, output high levels (v oh ) are equal to v ccq - 0.2v (not v cc ). for 2.7v - 3.6v output levels, v ccq must be tied to v cc . for 1.8v - 2.2v output levels, v ccq must be regulated to 2.0v 10%, while v cc must be regulated to 2.7v - 3.0v (for minimum power).
11 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 figure 1. data polling algorithm (configuration register = 00) notes: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. i/o7 should be rechecked even if i/o5 = ?1? because i/o7 may change simultaneously with i/o5. start read i/o7 - i/o0 addr = va i/o7 = data? i/o3, i/o5 = 1? read i/o7 - i/o0 addr = va i/o7 = data? program/erase operation not successful, write product id exit command no no no yes yes yes program/erase operation successful, device in read mode figure 2. data polling algorithm (configuration register = 01) note: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful no no no yes yes yes
12 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 figure 3. toggle bit algorithm (configuration register = 00) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful no no no yes yes yes figure 4. toggle bit algorithm (configuration register = 01) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, write product id exit command no no no yes yes yes
13 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 notes: 1. i/o5 switches to a ?1? when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. i/o3 switches to a ?1? when the v pp level is not high enough to successfully perform program and erase operations. status bit table status bit i/o7 i/o7 i/o6 i/o5 (1) i/o3 (2) i/o2 rdy/busy configuration register 00 01 00/01 00/01 00/01 00/01 00/01 programming i/o7 0toggle0010 erasing 0 0 toggle 0 0 toggle 0 erase suspended & read erasing sector 11100toggle1 erase suspended & read non-erasing sector data data data data data data 1 erase suspended & program non-erasing sector i/o7 0 toggle 0 0 toggle 0
14 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 notes: 1. the data format shown for each bus cycle is as follows; i/o7 - i/o0 (hex). in word operation i/o15 - i/o8 are don?t care. the address format shown for each bus cycle is as follows: a11 - a0 (hex). address a20 through a11 are don?t care in the word mode. 2. since a11 is a don?t care, aaa can be replaced with 2aa. 3. sa = sector address. any word address within a sector can be used to designate the sector address (see pages 18-17 for details). 4. once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 5. either one of the product id exit commands can be used. 6. if data bit d1 is ?0?, block b is locked. if data bit d1 is ?1?, block b can be reprogrammed. 7. the default state (after power-up) of the configuration register is ?00?. 8. bytes of data other than f0 may be used to exit the product id mode. however, it is recommended that f0 be used. command definition in hex (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 555 10 sector erase 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (3)(4) 30 word program 4 555 aa aaa 55 555 a0 addr d in enter single pulse program mode 6 555 aa aaa 55 555 80 555 aa aaa 55 555 a0 single pulse word program 1addrd in sector lockdown 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 sa (3)(4) 60 erase/program suspend 1 xxx b0 erase/program resume 1 xxx 30 product id entry 3 555 aa aaa 55 555 90 product id exit (5) 3 555 aa aaa 55 555 f0 (8) product id exit (5) 1 xxx f0 (8) program protection register 4 555 aa aaa 55 555 c0 addr d in lock protection register - block b 4 555 aa aaa 55 555 c0 080 x0 status of block b protection 4 555 aa aaa 55 555 90 80 d out (6) set configuration register 4 555 aa aaa 55 555 d0 xxx 00/01 (7) absolute maximum ratings* temperature under bias................................. -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground .................................. -0.6v to +6.25v all output voltages with respect to ground ............................ -0.6v to v cc + 0.6v voltage on v pp with respect to ground .................................. -0.6v to +13.0v
15 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 note: all address lines not specified in the above table must be ?0? when accessing the protection register, i.e., a20 - a8 = 0. protection register addressing table word use block a7 a6 a5 a4 a3 a2 a1 a0 0 factory a 10000001 1 factory a 10000010 2 factory a 10000011 3 factory a 10000100 4 user b 10000101 5 user b 10000110 6 user b 10000111 7 user b 10001000
16 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 bottom boot ? sector address table sector x16 address range (a20 - a0) sa0 00000 - 00fff sa1 01000 - 01fff sa2 02000 - 02fff sa3 03000 - 03fff sa4 04000 - 04fff sa5 05000 - 05fff sa6 06000 - 06fff sa7 07000 - 07fff sa8 08000 - 0ffff sa9 10000 - 17fff sa10 18000 - 1ffff sa11 20000 - 27fff sa12 28000 - 2ffff sa13 30000 - 37fff sa14 38000 - 3ffff sa15 40000 - 47fff sa16 48000 - 4ffff sa17 50000 - 57fff sa18 58000 - 5ffff sa19 60000 - 67fff sa20 68000 - 6ffff sa21 70000 - 77fff sa22 78000 - 7ffff sa23 80000 - 87fff sa24 88000 - 8ffff sa25 90000 - 97fff sa26 98000 - 9ffff sa27 a0000 - a7fff sa28 a8000 - affff sa29 b0000 - b7fff sa30 b8000 - bffff sa31 c0000 - c7fff sa32 c8000 - cffff sa33 d0000 - d7fff sa34 d8000 - dffff sa35 e0000 - e7fff sa36 e8000 - effff
17 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 sa37 f0000 - f7fff sa38 f8000 - fffff sa39 100000 - 107fff sa40 108000 - 10ffff sa41 110000 - 117fff sa42 118000 - 11ffff sa43 120000 - 127fff sa44 128000 - 12ffff sa45 130000 - 137fff sa46 138000 - 13ffff sa47 140000 - 147fff sa48 148000 - 14ffff sa49 150000 - 157fff sa50 158000 - 15ffff sa51 160000 - 167fff sa52 168000 - 16ffff sa53 170000 - 177fff sa54 178000 - 17ffff sa55 180000 - 187fff sa56 188000 - 18ffff sa57 190000 - 197fff sa58 198000 - 19ffff sa59 1a0000 - 1a7fff sa60 1a8000 - 1affff sa61 1b0000 - 1b7fff sa62 1b8000 - 1bffff sa63 1c0000 - 1c7fff sa64 1c8000 - 1cffff sa65 1d0000 - 1d7fff sa66 1d8000 - 1dffff sa67 1e0000 - 1e7fff sa68 1e8000 - 1effff sa69 1f0000 -1f7fff sa70 1f8000 - 1ffff bottom boot ? sector address table (continued) sector x16 address range (a20 - a0)
18 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 top boot ? sector address table sector x16 address range (a20 - a0) sa0 00000 - 07fff sa1 08000 - 0ffff sa2 10000 - 17fff sa3 18000 - 1ffff sa4 20000 - 27fff sa5 28000 - 2ffff sa6 30000 - 37fff sa7 38000 - 3ffff sa8 40000 - 47fff sa9 48000 - 4ffff sa10 50000 - 57fff sa11 58000 - 5ffff sa12 60000 - 67fff sa13 68000 - 6ffff sa14 70000 - 77fff sa15 78000 - 7ffff sa16 80000 - 87fff sa17 88000 - 8ffff sa18 90000 - 97fff sa19 98000 - 9ffff sa20 a0000 - a7fff sa21 a8000 - affff sa22 b0000 - b7fff sa23 b8000 - bffff sa24 c0000 - c7fff sa25 c8000 - cffff sa26 d0000 - d7fff sa27 d8000 - dffff sa28 e0000 - e7fff sa29 e8000 - effff sa30 f0000 - f7fff sa31 f8000 - fffff sa32 100000 - 107fff sa33 108000 - 10ffff sa34 110000 - 117fff sa35 118000 - 11ffff sa36 120000 - 127fff
19 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 sa37 128000 - 12ffff sa38 130000 - 137fff sa39 138000 - 13ffff sa40 140000 - 147fff sa41 148000 - 14ffff sa42 150000 - 157fff sa43 158000 - 15ffff sa44 160000 - 167fff sa45 168000 - 16ffff sa46 170000 - 177fff sa47 178000 - 17ffff sa48 180000 - 187fff sa49 188000 - 18ffff sa50 190000 - 197fff sa51 198000 - 19ffff sa52 1a0000 - 1a7fff sa53 1a8000 - 1affff sa54 1b0000 - 1b7fff sa55 1b8000 - 1bffff sa56 1c0000 - 1c7fff sa57 1c8000 - 1cffff sa58 1d0000 - 1d7fff sa59 1d8000 - 1dffff sa60 1e0000 - 1e7fff sa61 1e8000 - 1effff sa62 1f0000 - 1f7fff sa63 1f8000 - 1f8fff sa64 1f9000 - 1f9fff sa65 1fa000 - 1fafff sa66 1fb000 - 1fbfff sa67 1fc000 - 1fcfff sa68 1fd000 - 1fdfff sa69 1fe000 - 1fefff sa70 1ff000 - 1fffff top boot ? sector address table (continued) sector x16 address range (a20 - a0)
20 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms on page 25. 3. v h = 12.0v 0.5v. 4. manufacturer code: 001fh (x16), device code: 00c8h (x16)-bottom boot; 00c9h (x16)-top boot. 5. see details under ?software product identification entry/exit? on page 27. 6. v ihpp (min) = 0.9v; v ihpp (max) = 3.6v. 7. v ilpp (max) = 0.4v. dc and ac operating range 32-mbit flash operating temperature (case) ind. -40c - 85c v cc power supply 2.7v to 3.6v operating modes mode ce oe we reset v pp ai i/o read v il v il v ih v ih xaid out program/erase (2) v il v ih v il v ih v ihpp (6) ai d in standby/program inhibit v ih x (1) xv ih x x high-z program inhibit xxv ih v ih x xv il xv ih x xxx v ih v ilpp (7) output disable x v ih xv ih x high-z reset xxx v il x x high-z product identification hardware v il v il v ih v ih a1 - a20 = v il , a9 = v h (3) , a0 = v il manufacturer code (4) a1 - a20 = v il , a9 = v h (3) , a0 = v ih device code (4) software (5) v ih a0 = v il , a1 - a20 = v il manufacturer code (4) a0 = v ih , a1 - a20 = v il device code (4)
21 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 note: 1. in the erase mode, i cc is 65 ma. dc characteristics symbol parameter condition min typ max units i li input load current v in = 0v to v cc 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb v cc standby current cmos ce = v cc - 0.3v to v cc 13 25 a i cc (1) v cc active read current f = 5 mhz; i out = 0 ma 12 25 ma i cc1 v cc programming current 45 ma i pp1 v pp input load current 10 a v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol1 output low voltage i ol = 2.1 ma 0.45 v v ol2 output low voltage i ol = 1.0 ma 0.20 v v oh1 output high voltage i oh = -400 a i oh = -400 a i oh = -400 a v ccq < 2.6v v ccq 2.6v v ccq - 0.2 2.4 2.4 v v v v oh2 output high voltage i oh = -100 a i oh = -100 a i oh = -100 a v ccq < 2.6v v ccq 2.6v v ccq - 0.1 2.5 2.5 v v v
22 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter 32-mbit flash units min max t rc read cycle time 70 ns t acc address to output delay 70 ns t ce (1) ce to output delay 70 ns t oe (2) oe to output delay 0 40 ns t df (3)(4) ce or oe to output float 0 25 ns t oh output hold from oe , ce or address, whichever occurred first 0ns t ro reset to output delay 100 ns output valid output high z reset oe toe tce address valid tdf toh tacc tro ce address trc
23 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 input test waveforms and measurement level t r , t f < 5 ns output test load note: this parameter is characterized and is not 100% tested. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
24 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 ac word load waveforms we controlled ce controlled ac word load characteristics symbol parameter min max units t as , t oes address, oe setup time 0 ns t ah address hold time 35 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )35ns t ds data setup time 35 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 35 ns
25 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 555. for sector erase, the address depends on what sector is to be erased. (see note 3 under ?command definitions in hex? on page 14.) 3. for chip erase, the data should be 10h, and for sector erase, the data should be 30h. program cycle characteristics symbol parameter min typ max units t bp word programming time 15 150 s t as address setup time 0ns t ah address hold time 35 ns t ds data setup time 35 ns t dh data hold time 0ns t wp write pulse width 35 ns t wph write pulse width high 35 ns t wc write cycle time 70 ns t rp reset pulse width 500 ns t ec chip erase cycle time 80 400 seconds t sec1 sector erase cycle time (4k word sectors) 0.3 3.0 seconds t sec2 sector erase cycle time (32k word sectors) 1.2 5.0 seconds t es erase suspend time 15 s t ps program suspend time 20 s oe program cycle input data address a0 55 555 555 aa aaa t bp t wph t wp ce we a0 - a20 data t as t ah t dh t ds 555 aa t wc oe (1) aa 80 note 3 55 55 555 555 note 2 aa word 0 word 1 word 2 word 3 word 4 word 5 aaa aaa t wph t wp ce we a0-a20 data t as t ah t ec t dh t ds 555 t wc
26 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ?ac read characteristics? on page 22. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ?ac read characteristics? on page 22. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns a0-a20 we ce oe i/o7 tdh toeh toe high z an an an an an twr toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 50 ns t wr write recovery time 0 ns
27 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 software product identification entry (1) software product identification exit (1)(6) notes: 1. data format: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (hex) address format: a11 - a0 (hex), and a11 - a20 (don?t care). 2. a1 - a20 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 001fh(x16) device code: 00c8 (x16)-bottom boot 00c9h (x16)-top boot. 6. either one of the product id exit commands can be used. load data aa to address 555 load data 55 to address aaa load data 90 to address 555 enter product identification mode (2)(3)(5) load data aa to address 555 load data 55 to address aaa load data f0 to address 555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) sector lockdown enable algorithm (1) notes: 1. data format: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (hex) address format: a11 - a0 (hex), a-1, and a11 - a20 (don?t care). 2. sector lockdown feature enabled. load data aa to address 555 load data 55 to address aaa load data 80 to address 555 load data aa to address 555 load data 55 to address aaa load data 60 to sector address pause 200 s (2)
28 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 4-megabit sram description the 4-megabit sram is a high-speed, super low-power cmos sram organized as 256k words by 16 bits. the sram uses high-performance full cmos process technology and is designed for high-speed and low-power circuit technology. it is particularly well-suited for the high-density low-power system application. this device has a data retention mode that guar- antees data to remain valid at a minimum power supply voltage of 1.2v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup ? 1.2v (min) data retention block diagram voltage (v) speed (ns) operation current/i cc (ma) (max) standby current (a) (max) temperature ( c) 2.7 - 3.3 70 3 10 -40 - 85 memory array 256k x 16 i/o0 sub slb soe scs2 scs1 swe data i/o buffer sense amp write driver i/o7 i/o8 i/o15 row decoder column decoder block decoder pre decoder add input buffer a0 a17
29 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 note: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. notes: 1. h = v ih , l = v il , x = don't care (v il or v ih ) 2. sub , slb (upper, lower byte enable). these active low inputs allow individual bytes to be written or read. when slb is low, data is written or read to the lower byte, i/o0 - i/o7. when sub is low, data is written or read to the upper byte, i/o8 - i/o15. note: 1. undershoot: v il = -1.5v for pulse width less than 30 ns. undershoot is sampled, not 100% tested. absolute maximum ratings (1) symbol parameter rating unit v in , v out input/output voltage -0.3 to 3.6 v v cc power supply -0.3 to 4.6 v t a operating temperature -40 to 85 c t stg storage temperature -55 to 150 c p d power dissipation 1.0 w truth table scs1 scs2 swe soe slb (2) sub (2) mode i/o pin power i/o0 - i/o7 i/o8 - i/o15 h (1) x xx xx deselected high-z high-z standby x (1) l xx hh l (1) hhh lh output disabled high-z high-z active hl ll lhlx lh write d in high-z active hl high-z d in ll d in d in d in high-z lhhl lh read d out high-z active hl high-z d out ll d out d out d out high-z recommended dc operating condition symbol parameter min typ max unit v cc supply voltage 2.7 3.0 3.3 v v ss ground 0 0 0 v v ih input high voltage 2.2 v cc + 0.3 v v il (1) input low voltage -0.3 (1) 0.6 v
30 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 note: 1. these parameters are sampled and not 100% tested. dc electrical characteristics t a = -40 c to 85 c symbol parameter test condition min max unit i li input leakage current v ss < v in < v cc -1 1 a i lo output leakage current v ss < v out < v cc , scs1 = v ih or scs2=v il or soe = v ih or swe = vil or sub = v ih , slb = v ih -1 1 a i cc operating power supply current scs1 = v il , scs2=v ih , v in = v ih or v il , i i/o = 0 ma 3ma i cc1 average operating current scs1 = v il , scs2 = v ih , v in = v ih or v il , cycle time = min 100% duty, i i/o = 0 ma 15 ma scs1 < 0.2v, scs2 > v cc - 0.2v v in < 0.2v or v in > v cc - 0.2v, cycle time = 1 s 100% duty, i i/o = 0 ma 2ma i sb standby current (ttl input) scs1 = v ih or scs2 = v il or sub , slb = v ih v in = v ih or v il 300 a i sb1 standby current (cmos input) scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 10 a v ol output low i ol = 2.1 ma 0.4 v v oh output high i oh = -1.0 ma 2.4 v capacitance (1) (temp = 25 c, f = 1.0 mhz) symbol parameter condition max unit c in input capacitance (add, scs1 , scs2, slb , sub , swe , soe ) v in = 0 v 8 pf c out output capacitance (i/o) v i/o = 0 v 10 pf
31 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 ac characteristics t a = -40 c to 85 c, unless otherwise specified # symbol parameter 70 ns unit min max 1t rc read cycle time 70 ns 2t aa address access time 70 ns 3t acs chip select access time 70 ns 4t oe output enable to output valid 35 ns 5t ba slb , sub access time 70 ns 6t clz chip select to output in low z 10 ns 7t olz output enable to output in low z 5 ns 8t blz slb , sub enable to output in low z 10 ns 9t chz chip deselection to output in high z 0 25 ns 10 t ohz out disable to output in high z 0 25 ns 11 t bhz slb , sub disable to output in high z 0 25 ns 12 t oh output hold from address change 10 ns 13 t wc write cycle time 30 ns 14 t cw chip selection to end of write 30 ns 15 t aw address valid to end of write 30 ns 16 t bw slb , sub valid to end of write 30 ns 17 t as address setup time 0 ns 18 t wp write pulse width 30 ns 19 t wr write recovery time 0 ns 20 t whz write to output in high z 0 20 ns 21 t dw data to write time overlap 20 ns 22 t dh data hold from write time 0 ns 23 t ow output active from end of write 5 ns ac test conditions ta = - 4 0 c to 85 c, unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5 ns input and output timing reference level 1.5v output load t clz , t olz , t blz , t chz , t ohz , t bhz , t whz , t ow cl = 5 pf + 1 ttl load others cl = 30 pf + 1 ttl load
32 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 ac test loads note: including jig and scope capacitance. d out 1728 ohm cl 1029 ohm v tm = 2.8v (1)
33 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 timing diagrams read cycle 1 (1) , (4) read cycle 2 (1) , (2) , (4) read cycle 3 (1) , (2) , (4) notes: 1. read cycle occurs whenever a high on the swe and soe is low, while sub and/or slb and scs1 and scs2 are in active status. 2. soe = v il . 3. transition is measured 200 mv from steady state voltage. this parameter is sampled and not 100% tested. 4. scs1 in high for the standby, low for active. scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address soe sub, slb scs1 scs2 data out high-z data valid t aa t rc t ba t acs t oe t olz t blz t clz t bhz t chz t oh t ohz (3) (3) (3) (3) (3) (3) data out address t aa previous data t oh data valid t oh t rc sub, slb scs1 scs2 data out t acs t clz (3) data valid t chz (3)
34 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 write cycle 1 (swe controlled) (1) , (4) , (8) write cycle 2 (scs1 , scs2 controlled) (1) , (4) , (8) notes: 1. a write occurs during the overlap of a low swe , a low scs1 , a high scs2 and a low sub and/or slb . 2. t wr is measured from the earlier of scs1 , slb , sub , or swe going high or scs2 going low to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the scs1 , slb and sub low transition and scs2 high transition occur simultaneously with the swe low transition or after the swe transition, outputs remain in a high impedance state. 5. q (data out) is the same phase with the write data of this write cycle. 6. q (data out) is the read data of the next address. 7. transition is measured 200 mv from steady state. this parameter is sampled and not 100% tested. 8. scs1 in high for the standby, low for active scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t whz t wr t dw t dh t ow data valid high-z t as (2) (5) (5) (3)(7) address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t wr t dw t dh data valid high-z (2) high-z
35 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 notes: 1. typical values are under the condition of t a = 25 c. typical values are sampled and not 100% tested. 2. t rc is read cycle time. data retention timing diagram 1 data retention timing diagram 2 data retention electric characteristic t a = -40 c to 85 c symbol parameter test condition min typ max unit v dr v cc for data retention scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 1.2 3.3 v i ccdr data retention current vcc=1.5v, scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 0.2 6 a t cdr chip deselect to data retention time see data retention timing diagram 0 ns t r operating recovery time t rc ns data retention mode t r t cdr vcc scs1 > vcc - 0.2v 2.7v ih vdr scs1 vss vcc 2.7v vdr scs2 vss 0.4v data retention mode t r t cdr scs2 < 0.2v
36 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 8-megabit sram description the 8-megabit sram is a high-speed, super low-power cmos sram organized as 512k words by 16 bits. the sram uses high-performance full cmos process technology and is designed for high-speed and low-power circuit technology. it is particularly well-suited for the high-density low-power system application. this device has a data retention mode that guar- antees data to remain valid at a minimum power supply voltage of 1.2v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup ? 1.2v (min) data retention block diagram voltage (v) speed (ns) operation current/i cc (ma) (max) standby current (a) (max) temperature ( c) 2.7 - 3.3 70 3 15 -40 - 85 memory array 512k x 16 i/o0 sub slb soe scs2 scs1 swe data i/o buffer sense amp write driver i/o7 i/o8 i/o15 row decoder column decoder block decoder pre decoder add input buffer a0 a18
37 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 note: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. notes: 1. h = v ih , l = v il , x = don't care (v il or v ih ) 2. sub , slb (upper, lower byte enable). these active low inputs allow individual bytes to be written or read. when slb is low, data is written or read to the lower byte, i/o0 - i/o7. when sub is low, data is written or read to the upper byte, i/o8 - i/o15. note: 1. undershoot: v il = -1.5v for pulse width less than 30 ns. undershoot is sampled, not 100% tested. absolute maximum ratings (1) symbol parameter rating unit v in , v out input/output voltage -0.3 to 3.6 v v cc power supply -0.3 to 4.6 v t a operating temperature -40 to 85 c t stg storage temperature -55 to 150 c p d power dissipation 1.0 w truth table scs1 scs2 swe soe slb (2) sub (2) mode i/o pin power i/o0 - i/o7 i/o8 - i/o15 h (1) x xx xx deselected high-z high-z standby x (1) l xx hh l (1) hhh lh output disabled high-z high-z active hl ll lhlx lh write d in high-z active hl high-z d in ll d in d in d in high-z lhhl lh read d out high-z active hl high-z d out ll d out d out d out high-z recommended dc operating condition symbol parameter min typ max unit v cc supply voltage 2.7 3.0 3.3 v v ss ground 0 0 0 v v ih input high voltage 2.2 v cc + 0.3 v v il (1) input low voltage -0.3 (1) 0.6 v
38 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 note: 1. these parameters are sampled and not 100% tested. dc electrical characteristics t a = -40 c to 85 c symbol parameter test condition min max unit i li input leakage current v ss < v in < v cc -1 1 a i lo output leakage current v ss < v out < v cc , scs1 = v ih or scs2=v il or soe = v ih or swe = vil or sub = v ih , slb = v ih -1 1 a i cc operating power supply current scs1 = v il , scs2=v ih , v in = v ih or v il , i i/o = 0 ma 3ma i cc1 average operating current scs1 = v il , scs2 = v ih , v in = v ih or v il , cycle time = min 100% duty, i i/o = 0 ma 15 ma scs1 < 0.2v, scs2 > v cc - 0.2v v in < 0.2v or v in > v cc - 0.2v, cycle time = 1 s 100% duty, i i/o = 0 ma 2ma i sb standby current (ttl input) scs1 = v ih or scs2 = v il or sub , slb = v ih v in = v ih or v il 0.3 ma i sb1 standby current (cmos input) scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 15 a v ol output low i ol = 2.1 ma 0.4 v v oh output high i oh = -1.0 ma 2.4 v capacitance (1) (temp = 25 c, f = 1.0 mhz) symbol parameter condition max unit c in input capacitance (add, scs1 , scs2, slb , sub , swe , soe ) v in = 0 v 8 pf c out output capacitance (i/o) v i/o = 0 v 10 pf
39 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 ac characteristics t a = -40 c to 85 c, unless otherwise specified # symbol parameter 70 ns unit min max 1t rc read cycle time 70 ns 2t aa address access time 70 ns 3t acs chip select access time 70 ns 4t oe output enable to output valid 35 ns 5t ba slb , sub access time 70 ns 6t clz chip select to output in low z 10 ns 7t olz output enable to output in low z 5 ns 8t blz slb , sub enable to output in low z 10 ns 9t chz chip deselection to output in high z 0 25 ns 10 t ohz out disable to output in high z 0 25 ns 11 t bhz slb , sub disable to output in high z 0 25 ns 12 t oh output hold from address change 10 ns 13 t wc write cycle time 70 ns 14 t cw chip selection to end of write 60 ns 15 t aw address valid to end of write 60 ns 16 t bw slb , sub valid to end of write 60 ns 17 t as address setup time 0 ns 18 t wp write pulse width 50 ns 19 t wr write recovery time 0 ns 20 t whz write to output in high z 0 20 ns 21 t dw data to write time overlap 30 ns 22 t dh data hold from write time 0 ns 23 t ow output active from end of write 5 ns ac test conditions ta = - 4 0 c to 85 c, unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5 ns input and output timing reference level 1.5v output load t clz , t olz , t blz , t chz , t ohz , t bhz , t whz , t ow cl = 5 pf + 1 ttl load others cl = 30 pf + 1 ttl load
40 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 ac test loads note: including jig and scope capacitance. d out 1728 ohm cl 1029 ohm v tm = 2.8v (1)
41 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 timing diagrams read cycle 1 (1) , (4) read cycle 2 (1) , (2) , (4) read cycle 3 (1) , (2) , (4) notes: 1. read cycle occurs whenever a high on the swe and soe is low, while sub and/or slb and scs1 and scs2 are in active status. 2. soe = v il . 3. transition is measured 200 mv from steady state voltage. this parameter is sampled and not 100% tested. 4. scs1 in high for the standby, low for active. scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address soe sub, slb scs1 scs2 data out high-z data valid t aa t rc t ba t acs t oe t olz t blz t clz t bhz t chz t oh t ohz (3) (3) (3) (3) (3) (3) data out address t aa previous data t oh data valid t oh t rc sub, slb scs1 scs2 data out t acs t clz (3) data valid t chz (3)
42 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 write cycle 1 (swe controlled) (1) , (4) , (8) write cycle 2 (scs1 , scs2 controlled) (1) , (4) , (8) notes: 1. a write occurs during the overlap of a low swe , a low scs1 , a high scs2 and a low sub and/or slb . 2. t wr is measured from the earlier of scs1 , slb , sub , or swe going high or scs2 going low to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the scs1 , slb and sub low transition and scs2 high transition occur simultaneously with the swe low transition or after the swe transition, outputs remain in a high impedance state. 5. q (data out) is the same phase with the write data of this write cycle. 6. q (data out) is the read data of the next address. 7. transition is measured 200 mv from steady state. this parameter is sampled and not 100% tested. 8. scs1 in high for the standby, low for active scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t whz t wr t dw t dh t ow data valid high-z t as (2) (5) (5) (3)(7) address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t wr t dw t dh data valid high-z (2) high-z
43 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 notes: 1. typical values are under the condition of t a = 25 c. typical values are sampled and not 100% tested. 2. t rc is read cycle time. data retention timing diagram 1 data retention timing diagram 2 data retention electric characteristic t a = -40 c to 85 c symbol parameter test condition min typ max unit v dr v cc for data retention scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 1.2 3.3 v i ccdr data retention current vcc = 3v, scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 18a t cdr chip deselect to data retention time see data retention timing diagram 0 ns t r operating recovery time t rc ns data retention mode t r t cdr vcc scs1 > vcc - 0.2v 2.7v ih vdr scs1 vss vcc 2.7v vdr scs2 vss 0.4v data retention mode t r t cdr scs2 < 0.2v
44 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 ordering information t acc (ns) ordering code flash boot block flash plane architecture sram package operation range 70 at52br3224a-70ci bottom 32m ? single bank 256k x 16 66c5 industrial (-40 to 85 c) 70 at52br3224at-70ci top 32m ? single bank 256k x 16 66c5 industrial (-40 to 85 c) 70 AT52BR3228A-70ci bottom 32m ? single bank 512k x 16 66c5 industrial (-40 to 85 c) 70 AT52BR3228At-70ci top 32m ? single bank 512k x 16 66c5 industrial (-40 to 85 c) package type 66c5 66-ball, plastic chip-size ball grid array package (cbga)
45 at52br3224a(t)/3228a(t) 3338b?stkd?6/03 packaging information 66c5 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 66c5 , 66-ball (12 x 8 array), 10 x 8 x 1.2 mm body, 0.8 mm ball pitch chip-scale ball grid array package (cbga) a 66c5 09/19/01 side view a a1 0.12 seating plane c c top view bottom view 0.60 ref e d a1 ball corner ?b marked a1 identifier a b c d e f g h 1 2 3 4 5 6 7 8 9 10 11 12 d1 1.20 ref e e e1 common dimensions (unit of measure = mm) symbol min nom max note e 9.90 10.00 10.10 e1 ? 8.80 ? d 7.90 8.00 8.10 d1 ? 5.60 ? a ? ? 1.20 a1 0.25 ? ? e 0.80 bsc ?b ? 0.40 ?
printed on recycled paper. 3338b?stkd?6/03 /xm disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products , expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature web site www.atmel.com ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof are the registered trademarks of atmel corporation or its subsidiaries. other terms and product nam es may be the trademarks of others.

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